Several emerging data transmission standards, such as MPHY by Mobile Industry Processor Interface (MIPI), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB) 3.0 and 5.0, Peripheral Component Interconnect (PCI) Express, 1 GB and 10 GB Ethernet, RapidIO, and Fiber Channel, have serial data transmission as their core technology. Recently, serial data transmission has become capable of delivering data transmission speeds in the range of 2-10 Gbps. Additionally, serial interfaces provide higher clock rates than other interfaces.
High-speed burst-mode serial links, such as M-PHY, have gained increasing interest in recent years. High-speed burst-mode serial links provide high power efficiency because the high-speed burst-mode serial links only enable a transmitter/receiver during a serial data burst. Unlike the continuous operation mode serial links, in high-speed burst-mode serial links the clock/data recovery (CDR) module has to promptly lock the data bits and the clock during the serial data burst. Conventional clock/data recovery (CDR) implementations, however, suffer from performance degradation due to reduced jitter tolerance.
Conventional clock/data recovery circuits also suffer from an increased start-up delay following a power down or standby of a receiver device. When everything is powered down, starting up and getting into a ready mode for transmission or reception state is time consuming. This time delay may be due to the process of locking and synchronizing the clocks as high-speed data communications solutions specify that the clocks are stable before reliable transmission.